1. Field of the Invention
The present invention relates to a circuit for reading data, and particularly, to a circuit for varying read timing by changing the phase of a clock signal, to correctly read data in synchronization with the phase-changed clock signal.
2. Description of the Related Art
A data signal can be successfully read if its stable zone can be accessed. It is necessary, therefore, to synchronize a rising or falling edge of a clock signal with the stable zone of the data signal. If the edge of the clock signal is adjusted to the rising or falling of the data signal, an indefinite zone of the data signal will be read and this will cause read errors.
The relationship between a clock signal and a data signal is influenced by a phase shift in the clock signal, the structure of the clock generator, manufacturing variations, temperatures, etc. These factors may cause a clock signal to coincide with an indefinite zone of a data signal and result in read errors.
To avoid this problem, delay lines and phase shifters are usually employed to adjust the relationship between a data signal and a clock signal during manufacture. The delay lines and phase shifters, however, are expensive and involve complicated circuits and installation work.